The present invention relates generally to a process for laminating high-layer-count (HLC) substrates and more particularly to a process for manufacturing a multilayer package of at least two HLC substrates having reliable electrical and mechanical connections.
The advent of high-density circuits has spurred the development and implementation of high-layer-count (HLC) printed wiring boards (PWBs) having multilayer substrates. While multilayer substrates typically offer the advantage of more efficient use of space in a circuit board design, multilayer substrates typically require more complex connection capabilities and circuit modularity. These complexities give rise to several problems. For one, relatively large drills often are required to form via holes, or xe2x80x9cvias,xe2x80x9d for connecting two or more HLC substrates to one another. Further, the alignment of layers and the potential for wander by the drill bit present serious obstacles to correct registration and connections between and among HLC substrates. Substrates with high aspect ratios introduce additional complications, as it generally is difficult to plate a via hole to connect multiple substrates without disturbing adjacent circuit features. Further, the interconnection between substrates typically cannot be easily repaired. As a result, the failure of a single connection may cause an entire multilayer package to be discarded as incurably defective.
In view of the problems presented in the use of HLC substrates (also known as large-layer-count substrates or LLC substrates) in multilayer packages, improved techniques for HLC lamination have been developed. For example, U.S. Pat. Nos. 5,786,238 and 5,986,339, both issued to Pai, et al., disclose techniques for HLC lamination based on plating copper and solder posts. While eliminating some of the problems discussed above, these techniques have a number of limitations. One such limitation includes the possibility of an electrical disconnect. It will be appreciated that the heights of plated posts on a large board often vary significantly from the edges to the center of the board despite the use of pulse plating processes and xe2x80x9cthievingxe2x80x9d features to enhance uniformity. Because of this height variation, some posts may fail to electrically connect with the counterpart on the opposing HLC substrate. These conventional techniques are also limited by the expense and time-requirements of the plating process, especially in small-batch production. It also will be appreciated that printed wiring boards (PWBs) with plated solder bumps typically are difficult to handle as solder slivers may separate from the plated bumps and cause problems in subsequent manufacturing operations unless the boards are reflowed to melt and secure the bumps.
Accordingly, an improved HLC laminating process would be advantageous.
The present invention mitigates or solves the above-identified limitations in known solutions, as well as other unspecified deficiencies in known solutions. A number of advantages associated with the present invention are readily evident to those skilled in the art, including economy of design and resources, transparent operation, cost savings, etc.
In accordance with one embodiment of the present invention, a multilayer package is provided. The multilayer package comprises a first high-layer-count (HLC) substrate including a first conductive pad and a first conductive layer disposed in the first HLC substrate and a first via extending through at least a portion of the first HLC substrate and providing an electrical connection between the first conductive pad and the first conductive layer. The multilayer package also comprises a second high-layer-count (HLC) substrate including a second conductive pad and a second conductive layer disposed in the second HLC substrate and a second via extending through at least a portion of the second HLC substrate and providing an electrical connection between the second conductive pad and the second conductive layer. The multilayer package further comprises an adhesive film disposed between the first HLC substrate and the second HLC substrate and having an aperture located at least in part between the first and second conductive pads, the adhesive film mechanically bonding the first HLC substrate and the second HLC substrate and a solder segment occupying at least a substantial portion of the aperture in the adhesive film and providing an electrical connection between the first conductive pad and the second conductive pad, the solder segment being formed at least in part by a reflow of solder paste applied to the first conductive pad.
In accordance with another embodiment of the present invention, a multilayer package is provided. The multilayer package comprises a first high-layer-count (HLC) substrate including a first conductive pad and a first conductive layer disposed in the first HLC substrate and a first via extending through at least a portion of the first HLC substrate and providing an electrical connection between the first conductive pad and the first conductive layer, wherein the first conductive pad is offset from an axis of the first via. The multilayer package further comprises a second high-layer-count (HLC) substrate including a second conductive pad and a second conductive layer disposed in the second HLC substrate and a second via extending through at least a portion of the second HLC substrate and providing an electrical connection between the second conductive pad and the second conductive layer. The multilayer package also comprises an adhesive film disposed between the first HLC substrate and the second HLC substrate and having an aperture located between the first and second conductive pads, the adhesive film mechanically bonding the first HLC substrate and the second HLC substrate and a solder segment occupying at least a substantial portion of the aperture in the adhesive film and providing an electrical connection between the first conductive pad and the second conductive pad, the solder segment being formed at least in part by a reflow of a solder bump formed on the first conductive pad.
In accordance with yet another embodiment of the present invention, a multilayer package is provided. The multilayer package comprises a first high-layer-count (HLC) substrate including a first conductive pad and a first conductive layer disposed in the first HLC substrate, the first conductive pad comprising a first pad section connected to a second pad section by a first connective portion and a first via extending through at least a portion of the first HLC substrate to the first pad section and providing an electrical connection between the first conductive pad and the first conductive layer. The multilayer package further comprises a second high-layer-count (HLC) substrate including a second conductive pad and a second conductive layer disposed on the second HLC substrate and a second via extending through at least a portion of the second HLC substrate and providing an electrical connection between the second conductive pad and the second conductive layer. The multilayer package additionally comprises an adhesive film disposed between the first HLC substrate and the second HLC substrate and having an aperture located substantially between the second pad section of the first conductive pad and the second conductive pad, the adhesive film mechanically bonding the first HLC substrate and the second HLC substrate and a solder segment occupying at least a substantial portion of the aperture in the adhesive film and providing an electrical connection between the first conductive pad and the second conductive pad, the solder segment being formed at least in part by a reflow of a solder bump formed on the second pad section.
In accordance with an additional embodiment of the present invention, a multilayer package is provided. The multilayer package comprises a first high-layer-count (HLC) substrate including a first conductive pad and a first conductive layer disposed in the first HLC substrate, an insulative layer disposed over at least a portion of the first conductive pad, the insulative layer including an aperture located over some but not all of the first conductive pad, and a first via extending through at least a portion of the first HLC substrate and providing an electrical connection between the first conductive pad and the first conductive layer. The multilayer package further comprises a second high-layer-count (HLC) substrate including a second conductive pad and a second conductive layer disposed in the second HLC substrate and a second via extending through at least a portion of the second HLC substrate and providing an electrical connection between the second conductive pad and the second conductive layer. The multilayer package also comprises an adhesive film disposed between the first HLC substrate and the second HLC substrate and having an aperture located substantially between the aperture in the insulative layer and the second conductive pad, the adhesive film mechanically bonding the first HLC substrate and the second HLC substrate and a solder segment occupying at least a substantial portion of the aperture in the adhesive film and providing an electrical connection between the first conductive pad and the second conductive pad, the solder segment being formed at least in part by a reflow of a solder bump formed on the second pad section.
In accordance with yet another embodiment of the present invention, a process for interconnecting at least two high-layer-count (HLC) laminates is provided. The process comprises the steps of forming a first via in a first HLC substrate and a second via in a second HLC substrate, the first via extending through at least a portion of the first HLC substrate to a bottom surface of the first HLC substrate and the second via extending through at least a portion of the second HLC substrate to a top surface of the second HLC substrate and forming a first conductive pad on the bottom surface of the first HLC substrate and a second conductive pad on the top surface of the second HLC substrate, the first conductive pad being in electrical contact with the first via and the second conductive pad being in electrical contact with the second via. The process further comprises the steps of applying solder paste to a surface of the first conductive pad, reflowing the solder paste to form a first solder bump on the first conductive pad and positioning an adhesive film between the bottom surface of the first HLC substrate and the top surface of the second HLC substrate, the adhesive film having an aperture substantially located between the first solder bump and the second conductive pad. The process further comprises the steps of pressing the first HLC substrate and the second HLC substrate together to adhere at least a portion of the bottom surface of the first HLC substrate to at least a portion of the top surface of the second HLC substrate and where the first solder bump occupies at least a portion of the aperture in the adhesive film and reflowing the first solder bump to form at least part of a solder segment providing an electrical connection between the first and second conductive pads.